Such memory cells with automatic refresh have been known which employ a voltage-switched FET capacitor, switched by the data stored, as for example in U.S. Pat. No. 3,691,537 to Burgess et al and a two-channel-region FET switch, controlled by the data stored, as in U.S. Pat. No. 4,112,510 to Baker. Other memory circuits with refresh are known of more general interest.
Illustrative of such prior art are U.S. Pat. No. 4,030,083 to Boll, in which a depletion-mode FET is the memory cell, in circuit with enhancement mode FETs, and U.S. Pat. No. 4,070,653 to Rao et al, which employs a voltage-switched resistor, switched by the data stored.
None of such known prior art employs a two-channel-region FET switch and a voltage-switched FET capacitor to block a refresh clock pulse at the capacitor when stored charge representing data is at one level and to steer a refresh clock pulse to a switch when the data is at the other level. This provides positive, error-free operation in a small-size, low-power memory. Such advantages are not believed to be achieved in the know prior art. Where a prior art circuit employs a design requiring precise, multiple input levels; high-precision fabrication; or large components, that design would not match the overall advantages of the subject FET memory with refresh. Because of the low power requirements, the subject circuit is well suited to use a standby battery for automatic protection of information in memory at power loss.